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91214hk 20130322-s00003/91609hkim no.a1335-1/24 http://onsemi.com * this product is licensed from silicon storage technology, inc. semiconductor components industries, llc, 2014 september, 2014 ver. 1.02 ordering information see detailed ordering and shipping informat ion on page 24 of this data sheet. lc87f2708a overview the lc87f2708a is an 8-bit microcotroller that, centered around a cpu running at a minimum bus cycle time of 100ns, integrates on a single chip a number of hardware features such as 8k-byte flash rom (onboard programmable), 512-byte ram, an on-chip debugger, a sophisticated 16- bit timer/counter (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers or pwms), a synchronous sio interface, a high-speed 12-bit pwm, two high-speed pulse width/period counters, a 7-channel ad converter with 12-/8-bit resolution selector, an analog comparator, a watchdog timer, an internal reset circuit, a system clock frequency divider, and a 16-source 10-vector interrupt feature. features flash rom - 8192 ? 8 bits - capable of on-board-programming with wide range of voltage source (3.0 to 5.5v). - block-erasable in 128-byte units ram - 512 ? 9 bits minimum bus cycle time note1 - 100ns (10mhz) v dd =2.7 to 5.5v note2 minimum instruction cycle time - 300ns (10mhz) v dd =2.7 to 5.5v note2 note1: the bus cycle time here refers to the rom read speed. note2: use this product in a voltage range of 3.0 to 5.5v because the minimum release voltage (porrl) of the power- on reset (por) circuit is 2.87v ? 0.12v. package form - mfp14s (pb-free / halogen free type) cmos lsi 8-bit microcontroller 8k-byte flash rom / 512-byte ram / 14-pin orderin g numbe r : ena1335b mfp14s(225mil) p31/intb/hct2in/dbgp01 p30/inta/hct1in/dbgpx0 res p10/so7/inte/an0/dbgp02 vss1 p16/intf/in1-/an6 p15/inte/in1+/an5/dbgp22 vdd1 p32/intc/cmpo/dbgp11 p33/intd/hpwm/dbgp12 p11/si7/sb7/inte/in0+/hct2in/an1 p12/sck7/intf/in0-/an2 p13/intf/t1pwml/an3/dbgp20 p14/inte/t1pwmh/an4/dbgp21 1 2 3 4 5 6 7 14 13 12 11 10 9 8
lc87f2708a no.a1335-2/24 ports - i/o ports ports whose i/o direction can be designated in 1 bit units: 11 (p10 to p16, p30 to p33) - reset pins: 1 (res#) - power pins: 2 (vss1, vdd1) timers - timer 0: 16-bit timer/counter with a capture register mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) mode 3: 16-bit counter (with a 16-bit capture register) - timer 1: 16-bit timer/counter that can provide with pwm/toggle output mode 0: 8-bit timer with an 8-bit prescaler (with toggle output) + 8-bit timer/counter with an 8-bit prescaler (with toggle output) mode 1: 8-bit pwm with an 8-bit prescaler ?? 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle output) (toggle output also possible from lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle output) (lower-order 8 bits may be used as pwm.) serial interface - sio7: 8-bit synchronous serial interface 1) lsb first/msb first mode selectable 2) built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tcyc) high-speed 12-bit pwm - system clock/high-speed rc oscillation cl ock (20mhz or 40mhz) operation selectable - duty/period programmable - continuous pwm output/specific count pwm output (automatic stop) selectable high-speed pulse width/period counter - hct1: high-speed pulse width/period counter 1 1) system clock/high-speed rc oscillation cl ock (20mhz or 40mhz) operation selectable 2) h-level width/l-level width/period measurement modes selectable 3) input triggering noise filter - hct2: high-speed pulse width/period counter 2 1) system clock/high-speed rc oscillation cl ock (20mhz or 40mhz) operation selectable 2) can measure both l-level width and period simultaneously. 3) input triggering noise filter 4) input trigger selectable (from 3 signals, i.e., p11/hct2in, p31/ hct2in, and analog comparator output) ad converter: 12 bits ? 7 channels - 12-/8-bit ad converter resolution selectable
lc87f2708a no.a1335-3/24 analog comparator - sends output to the p32/cmpo port (polarity selectable). - edge detection function (shared with intc and also allows the selection of the noise filter function) watchdog timer - can generate the internal reset signal on a timer overflow monitored by the wdt-dedicated low-speed rc oscillation clock (30khz). - allows selection of continue, stop, or hold mode operation of the counter on entry into the halt/ hold mode. interrupt source flags - 16 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x)) of multiplex interrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l inta 2 0000bh x or l intb 3 00013h h or l intc/t0l/inte 4 0001bh h or l intd/intf 5 00023h h or l t0h/sio7 6 0002bh h or l t1l/t1h 7 00033h h or l hct1 8 0003bh h or l hct2 9 00043h h or l adc/hpwm automatic stop/hpwm cycle 10 0004bh h or l none - priority levels x > h > l - of interrupts of the same level, the one with the smallest vector address takes precedence. subroutine stack levels: 256 levels maxi mum (the stack is allocated in ram.) high-speed multiplication/division instructions - 16 bits 8 bits (5 tcyc execution time) - 24 bits 16 bits (12 tcyc execution time) - 16 bits 8 bits (8 tcyc execution time) - 24 bits 16 bits (12 tcyc execution time) oscillation circuits - medium speed rc oscillation circuit (internal): for system clock (1mhz) - low speed rc oscillation circuit (internal): for watchdog timer (30khz) - high speed rc oscillation circuit (internal): for system clock (20mhz or 40mhz) 1) 2 source oscillation frequencies (20mhz or 40m hz) selectable for the high-speed rc oscillation circuit by optional configuration. system clock divider function - can run on low current. - the minimum instruction cycle selectable from 300ns, 600ns, 1.2 ? s, 2.4 ? s, 4.8 ? s, 9.6 ? s, 19.2 ? s, 38.4 ? s, and 76.8 ? s (when high speed rc oscillation is selected for system clock.).
lc87f2708a no.a1335-4/24 internal reset circuit - power-on reset (por) function 1) por reset is generated only at power-on time. 2) the por release level can be selected from 3 levels (2.87v, 3.86v, and 4.35v) by optional configuration. - low-voltage detection reset (lvd) function 1) lvd and por functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) the use or disuse of the lvd function and the low voltage threshold level (3 levels: 2.81v, 3.79v, and 4.28v) can be selected by optional configuration. standby function - halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) there are the following three ways of resetting the halt mode. <1> setting the reset pin to the low level <2> generating a reset signal via the watchdog timer or brown-out detector <3> having an interrupt generated - hold mode: suspends instruction execution a nd the operation of the peripheral circuits. 1) the medium- and high-speed rc oscillation circuits automatically stop operation. 2) there are the following four ways of resetting the hold mode. <1> setting the reset pin to the low level <2> generating a reset signal via the watchdog timer or brown-out detector <3> setting at least one of the inta, intb, intc, intd, inte, and intf pins to the specified level (inta and intb hold mode reset is av ailable only when level detection is set.) <4> applying input signals to the in+ and in ? pins so that the analog comparator output is set to the specified level (when the analog comparator output is assigned to the intc input) on-chip debugger function - supports software debugging with the ic mounted on the target board (lc87d2708a). lc87f2708a has an on-chip debugge r but its function is limited. - 3 channels of on-chip debugger pins are available. data security function note3 - protects the program data stored in flash memory from unauthorized read or copy. note3: this data security function does not necessarily provide absolute data security. development tools - on-chip debugger: 1) tcb87-type b + lc87d2708a 2) tcb87-type b + lc87f2708a 3) tcb87-type c (3 wire version) + lc87d2708a 4) tcb87-type c (3 wire version) + lc87f2708a
lc87f2708a no.a1335-5/24 programming board package programming board mfp14s w87f27m-dbg flash rom programming board maker model version device flash support group, inc. (fsg) + on semiconductor (note 4) in-circuit programmer af9101/af9103 (main body) (fsg models) (note 5) lc87f2708a sib87 (inter face driver) (on semiconductor model) on semiconductor single/gang programmer skk-dbg type b (sanyofws) application version 1.04 or later chip data version 2.10 or later lc87f2708a in-circuit/ gang programmer for information about af-series: flash support group, inc. tel: +81-53-459-1050 e-mail: sales@j-fsg.co.jp note4: on-board-programmer from fsg (a f9101/af9103) and serial interface dr iver from on semiconductor (sib87) together can give a pc-less, standa lone on-board-progr amming capabilities. note5: it needs a special programming de vices and applications depending on the use of programming environment. please ask fsg or on semiconductor for the information.
lc87f2708a no.a1335-6/24 package dimensions unit : mm soic14 w / mfp14s (225 mil) case 751cb issue a soldering footprint* note: the measurements are not to guarantee but for reference only. *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. (unit: mm) 5.70 0.47 1.10 1.00 xxxxx = specific device code y = year m = month ddd = additional traceability data generic marking diagram* *this information is generic. please refer to device data sheet for actual part marking. may or may not be present. xxxxxxxxxx ymddd
lc87f2708a no.a1335-7/24 pin assignment mfp14s (pb-free / halogen free type) mfp14s name 1 p31/intb/hct2in/dbgp01 2 p30/inta/hct1in/dbgpx0 3 res 4 p10/so7/inte/an0/dbgp02 5 vss1 6 p16/intf/in1-/an6 7 p15/inte/in1+/an5/dbgp22 8 p14/inte/t1pwmh/an4/dbgp21 9 p13/intf/t1pwml/an3/dbgp20 10 p12/sck7/intf/in0-/an2 11 p11/si7/sb7/inte/in0+/hct2in/an1 12 p33/intd/hpwm/dbgp12 13 p32/intc/cmpo/dbgp11 14 vdd1 p31/intb/hct2in/dbgp01 p30/inta/hct1in/dbgpx0 res p10/so7/inte/an0/dbgp02 vss1 p16/intf/in1-/an6 p15/inte/in1+/an5/dbgp22 vdd1 p32/intc/cmpo/dbgp11 p33/intd/hpwm/dbgp12 p11/si7/sb7/inte/in0+/hct2in/an1 p12/sck7/intf/in0-/an2 p13/intf/t1pwml/an3/dbgp20 p14/inte/t1pwmh/an4/dbgp21 1 2 3 4 5 6 7 14 13 12 11 10 9 8
lc87f2708a no.a1335-8/24 system block diagram interrupt control standby control ir pla flash rom pc bus interface port 1 (inte-intf) port 3 (inta-intd) sio7 timer 0 timer 1 high-speed pwm high-speed pulse width/period counter1 adc high-speed pulse width/period counter2 acc b register c register psw rar ram stack pointer alu on-chip debugger medium- speed rc freq. divider clock generator reset circuit (lvd/por) wdt (low-speed rc) reset control res# data bus data bus analog comparator high-speed rc
lc87f2708a no.a1335-9/24 pin description pin name i/o description option vss1 ? ? power supply pin no vdd1 ? + power supply pin no port1 p10 to p16 i/o - 7-bit i/o port - i/o specifiable in 1-bit units - pull-up resistors can be turned on and off in 1-bit units - multiplexed pins p10: sio7 data output p11: sio7 data input/bus i/o /high-speed pulse width/period counter 2 input p12: sio7 clock i/o p13: timer 1 pwml output p14: timer 1 pwmh output p10, p11, p14, p15: inte input/hold release input/timer 1 event input /timer 0l capture input/timer 0h capture input p12, p13, p16: intf input/hold release input/timer 1 event input /timer 0l capture input/timer 0h capture input ad converter input port: an0 to an6(p10 to p16) analog comparator input port 0: in0+, in0-(p11, p12) analog comparator input port 1: in1+, in1-(p15, p16) on-chip debugger pin 1: dbgp02 (p10) on-chip debugger pin 3: dbgp20 to dbgp22 (p13 to p15) - interrupt acknowledge type rising falling rising & falling h level l level inte ? ? ? ? ? intf ? ? ? ? ? yes port3 p30 to p33 i/o - 4-bit i/o port - i/o specifiable in 1-bit units - pull-up resistors can be turned on and off in 1-bit units - multiplexed pins p30: inta input/hold release input/timer 0l capture input /high-speed pulse width/period counter 1 input p31: intb input/hold release input/timer 0h capture input /high-speed pulse width/period counter 2 input p32: intc input/hold release input/timer 0 event input /timer 0l capture input/analog comparator output p33: intd input/hold release input/timer 0 event input /timer 0h capture input/high-speed pwm output on-chip debugger pin 1: dbgpx0 to dbgp01(p30 to p31) on-chip debugger pin 2: dbgpx0 to dbgp12(p30, p32 to p33) - interrupt acknowledge type rising falling rising & falling h level l level inta ? ? ? ? ? intb ? ? ? ? ? intc ? ? ? ? ? intd ? ? ? ? ? yes res i/o external reset input/internal reset output no
lc87f2708a no.a1335-10/24 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor p10 to p16 1 bit 1 cmos programmable 2 n-channel open drain programmable p30 to p33 1 bit 1 cmos programmable 2 n-channel open drain programmable on-chip debugger pin processing for the processing of the on-chip debugger pins, refer to the separately available documents entitled "rd87 on-chip debugger installation" and "lc872000 se ries on-chip debugger pin processing." recommended unused pin connections pin name recommended unused pin connections board software p10 to p16 open set output low p30 to p33 open set output low user options option name option type flash version option switched in unit of description port output type p10 to p16 ? 1bit cmos n-channel open drain p30 to p33 ? 1bit cmos n-channel open drain program start address ? ? ? 00000h 01e00h brown-out detector reset function brown-out detector function ? ? enable: used disable: not used brown-out trip level ? ? 3 levels power-on-reset function power-on-reset level ? ? 3 levels high-speed rc oscillator circuit oscillation frequency ? ? 20 mhz 40 mhz
lc87f2708a no.a1335-11/24 1. absolute maximum ratings at ta=25 ? c, v ss 1=0v parameter symbol pin/remarks conditions specification v dd [v] min. typ. max. unit maximum supply voltage v dd max vdd1 ? ? ? port 1 ? port 3 ? ? cmos output selected ? per applicable pin ? ? cmos output selected ? per applicable pin ? ? cmos output selected ? per applicable pin ? ? cmos output selected ? per applicable pin ? ? ioah(1) ? ports 10, 15, 16 ? ports 30, 31 total of currents at all applicable pins ? ? ioah(2) ? ports 11 to 14 ? ports 32, 33 total of currents at all applicable pins ? ? ioah(3) ? port 1 ? port 3 total of currents at all applicable pins ? ? ioal(1) ? port 10 ? ports 30, 31 total of currents at all applicable pins 25 ? ioal(2) ? ports 11 to 16 ? ports 32, 33 total of currents at all applicable pins 35 ? ioal(3) ? port 1 ? port 3 total of currents at all applicable pins 55 power dissipation pdmax(1) mfp14s ? ta= ? ? c ? independent package 113 mw pdmax(2) ? ta= ? ? c ? mounted on thermal test board ? (note 1-2) 260 operating ambient temperature topr ? ? c storage ambient temperature tstg ? ?? 114.3 ?? 1.6 tmm, glass epoxy board). stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected.
lc87f2708a no.a1335-12/24 2. allowable operating conditions at ta= ? 40 to +85 ? c, v ss 1=0v parameter symbol pin/remarks conditions specification v dd [v] min. typ. max. unit operating supply voltage (note 2-1) v dd vdd1 0.272 ? tcyc 100 ? ? port 1 ? port 3 output disabled 2.7 to 5.5 0.3v dd +0.7 v dd vih(2) res# 2.7 to 5.5 0.75v dd v dd low level input voltage vil(1) ? port 1 ? port 3 output disabled 4.0 to 5.5 v ss 0.1v dd +0.4 2.7 to 4.0 v ss 0.2v dd vil(2) res# 2.7 to 5.5 v ss 0.25v dd instruction cycle time (note 2-2) tcyc 2.7 to 5.5 0.272 100 ? ? high-speed rc oscillation ? 40mhz selected as option ? ta= ? 20 to +85 ? c 4.5 to 5.5 38 40 42 mhz fmhrc(2) ? high-speed rc oscillation ? 40mhz selected as option ? ta= ? 40 to +85 ? c 4.5 to 5.5 37.6 40 42.4 fmhrc(3) 3.5 to 5.5 36.8 40 43.2 fmhrc(4) 2.7 to 5.5 32 40 43.2 fmhrc(5) ? high-speed rc oscillation ? 20mhz selected as option ? ta= ? 20 to +85 ? c 3.0 to 5.5 19 20 21 fmhrc(6) ? high-speed rc oscillation ? 20mhz selected as option ? ta= ? 40 to +85 ? c 2.7 to 5.5 18.7 20 21.3 fmrc medium-speed rc oscillation 2.7 to 5.5 0.5 1.0 2.0 fmslrc low-speed rc oscillation 2.7 to 5.5 15 30 60 khz oscillation stabilization time tmshrc ? when high-speed rc oscillation state is switched from stopped to enabled. ? see fig. 2. 2.7 to 5.5 100 ? ? 0.12v. note 2-2: relationship between tcyc and oscillation frequency is as follows: - when system clock source is set to medium-speed rc oscillation 3/fmrc at a division ratio of 1/1, 6/fmrc at a division ra tio of 1/2, 12/fmrc a division ratio of 1/4, and so forth - when system clock source is set to high-speed rc os cillation (40mhz selected by optional configuration) 12/fmhrc at a division ratio of 1/1, 24/fmhrc at a division ratio of 1/2, 48/fmhrc a division ratio of 1/4, and so forth - when system clock source is set to high-speed rc os cillation (20mhz selected by optional configuration) 6/fmhrc at a division ratio of 1/1, 12/fmhrc at a divisi on ratio of 1/2, 24/fmhrc a division ratio of 1/4, and so forth functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
lc87f2708a no.a1335-13/24 3. electrical characteristics at ta= ? 40 to +85 ? c, v ss 1=0v parameter symbol pin/remarks conditions specification v dd [v] min. typ. max. unit high level input current iih(1) ? port 1 ? port 3 ? output disabled ? pull-up resistor off ? v in =v dd (including output tr. off leakage current) 2.7 to 5.5 1 ? ? port 1 ? port 3 ? output disabled ? pull-up resistor off ? v in =v ss (including output tr. off leakage current) 2.7 to 5.5 ? ? ? ? ? ? ? ? ? ? port 1 ? port 3 voh=0.9v dd 4.5 to 5.5 15 35 80 k ? rpu(2) 2.7 to 4.5 18 50 150 rpu(3) res# 2.7 to 5.5 216 360 504 hysteresis voltage vhys ? port 1 ? port 3 ? res# 2.7 to 5.5 0.1v dd v pin capacitance cp all pins ? v in =v ss for pins other than that under test ? f=1mhz ? ta=25 ? c 2.7 to 5.5 10 pf product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
lc87f2708a no.a1335-14/24 4. serial i/o characteristics at ta= ? 40 to +85 ? c, v ss 1=0v 4-1. sio7 serial i/o characteristics (note 4-1-1) parameter symbol pin/remarks conditions specification v dd [v] min. typ. max. unit serial clock input clock frequency tsck(1) sck7(p12) ? see fig. 4. (note 4-1-2) 2.7 to 5.5 2 tcyc low level pulse width tsckl(1) 1 high level pulse width tsckh(1) 1 output clock frequency tsck(2) sck7(p12) ? cmos output selected ? see fig. 4. 2.7 to 5.5 4/3 low level pulse width tsckl(2) 1/2 tsck high level pulse width tsckh(2) 1/2 serial input data setup time tsdi(1) sb7(p11), si7(p11) ? must be specified with respect to rising edge of sioclk. ? see fig. 4. 2.7 to 5.5 0.03 ? ? must be specified with respect to rising edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 4. 2.7 to 5.5 1tcyc +0.05 output clock tddo(2) (1/3)tcyc +0.05 note 4-1-1: these specifications are theoretic al values. add margin depending on its use. note 4-1-2: to use serial-clock-input in transmission/reception mode, the time from si7run being set when serial clock is "h" to the first falling edge of the serial clock must be longer than 1tcyc.
lc87f2708a no.a1335-15/24 5. pulse input conditions at ta= ? 40 to +85 ? c, v ss 1=0v parameter symbol pin/remarks conditions specification v dd [v] min. typ. max. unit high/low level pulse width tpih(1) tpil(1) inta(p30), intb(p31), intd(p33), inte (p10, p11, p14, p15), intf (p12, p13, p16) ? interrupt source flag can be set. ? event inputs for timers 0 and 1 are enabled. 2.7 to 5.5 1 tcyc tpih(2) tpil(2) intc(p32) when noise filter time constant is "none" ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 1 tpih(3) tpil(3) intc(p32) when noise filter time constant is "1/16" ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 64 tpih(4) tpil(4) intc(p32) when noise filter time constant is "1/32" ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 128 tpih(5) tpil(5) intc(p32) when noise filter time constant is "1/64" ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 5.5 256 tpih(6) tpil(6) hct1in(p30) pulses can be recognized as signals by the high-speed pulse width/period counter 1. 2.7 to 5.5 3 h1ck (note 5-1) tpih(7) tpil(7) hct2in(p11, p31) pulses can be recognized as signals by the high-speed pulse width/period counter 2. 2.7 to 5.5 6 h2ck (note 5-2) tpil(8) res# resetting is enabled. 2.7 to 5.5 200 ? ?? high-speed rc oscillation clock or system clock) for the high-speed pulse width/period counter 1. note 5-2: h2ck denotes the period of the base clock (2 to 16 ?? high-speed rc oscillation clock or system clock) for the high-speed pulse width/period counter 2. 6. comparator characteristics at ta= ? 40 to +85 ? c, v ss 1=0v parameter symbol pin/remarks conditions specification v dd [v] min. typ. max. unit common mode input voltage range vcmin in0+(p11), in0 ? (p12), in1+(p15), in1 ? (p16) 2.7 to 5.5 v ss v dd ? 1.5 v offset voltage voff within common mode input voltage range 2.7 to 5.5 ? 10 ? 30 mv response time trt ? within common mode input voltage range ? input amplitude=100mv ? overdrive=50mv 2.7 to 5.5 200 600 ns operation stabilization time (note 6-1) tcmw 2.7 to 5.5 1.0 ?
lc87f2708a no.a1335-16/24 7. ad converter characteristics at v ss 1=0v < 12-bit ad conversion mode at ta= ? 40 to +85 ? c > parameter symbol pin/remarks conditions specification v dd [v] min. typ. max. unit resolution n an0(p10) to an6(p16) 3.0 to 5.5 12 bit absolute accuracy et (note7-1) 3.0 to 5.5 ? 16 lsb conversion time tcad ? see "conversion time calculation method." ? (note7-2) 4.0 to 5.5 38 104.3 ? ? ? < 8-bit ad conversion mode at ta= ? 40 to +85 ? c > parameter symbol pin/remarks conditions specification v dd [v] min. typ. max. unit resolution n an0(p10) to an6(p16) 3.0 to 5.5 8 bit absolute accuracy et (note7-1) 3.0 to 5.5 ? 1.5 lsb conversion time tcad ? see "conversion time calculation method." ? (note7-2) 4.0 to 5.5 23.4 64.3 ? ? ? ?? (1/3) ?? tcyc 8-bit ad conversion mode: tcad (conversion time) = ((32/(division ratio)) + 2) ?? (1/3) ?? tcyc < recommended operating conditions > high-speed rc oscillation (fmhrc) supply voltage range (v dd ) system clock division ratio (sysdiv) cycle time (tcyc) ad division ratio (addiv) conversion time (tcad) 12-bit ad 8-bit ad 40mhz/20mhz 4.0v to 5.5v 1/1 300ns 1/8 41.8 ? s 25.8 ? s 3.0v to 5.5v 1/1 300ns 1/16 83.4 ? s 51.4 ? s note 7-1: the quantization error (1/2lsb) is excluded from the absolute accuracy. the absolute accuracy is measured when no change occurs in the i/o state of the pins that are adjacent to the analog input channel during ad conversion processing. note 7-2: the conversion time refers to the interval from th e time a conversion starting instruction is issued till the time the complete digital conversion value against the an alog input value is loaded in the result register. * the conversion time is twice the normal value when one of the following conditions occurs: - the first ad conversion execute d in the 12-bit ad conversion mode after a system reset. - the first ad conversion executed after the ad conversi on mode is switched from 8-bit to 12-bit ad conversion mode.
lc87f2708a no.a1335-17/24 8. power-on reset (por) characteristics at ta= ? 40 to +85 ? c, v ss 1=0v parameter symbol pin/remarks conditions specification option selecting voltage min. typ. max. unit por release voltage porrl ? option selected ? see fig. 6. (note 8-1) 2.87v 2.75 2.87 2.99 v 3.86v 3.73 3.86 3.99 4.35v 4.21 4.35 4.49 unknown voltage area pouks ? see fig. 6. (note 8-2) 0.7 0.95 power startup time poris power startup time from v dd =0v to 2.8v 100 ms note 8-1: the por release voltage can be selected from three levels when the low-voltage detection feature is deselected. note 8-2: there is an unpredictable period before the power-on reset transistor starts to turn on. 9. low-voltage detection (lvd) characteristics at ta= ? 40 to +85 ? c, v ss 1=0v parameter symbol pin/remarks conditions specification option selecting voltage min. typ. max. unit lvd reset voltage (note 9-2) lvdet ? option selected ? see fig. 7. (note 9-1) (note 9-3) 2.81v 2.71 2.81 2.91 v 3.79v 3.69 3.79 3.89 4.28v 4.18 4.28 4.38 lvd voltage hysteresis lvhys 2.81v 60 mv 3.79v 65 4.28v 65 unknown voltage area lvuks ? see fig. 7. (note 9-4) 0.7 0.95 v minimum low voltage detection width (response sensitivity) tlvdw ? lvdet-0.5v ? see fig. 8. 0.2 ms note 9-1: the lvd reset voltage can be selected from three levels when the low-voltage detection feature is selected. note 9-2: the hysteresis voltage is not included in the lvd reset voltage value. note 9-3: there are cases when the lvd reset voltage value is exceeded when a greater change in the output level or large current is applied to the port. note 9-4: there is an unpredictable period before the low-voltage detection resetting transistor starts to run.
lc87f2708a no.a1335-18/24 10. consumption current characteristics at ta= ? 40 to +85 ? c, v ss 1=0v note 10-1: the consumption current value includes none of the currents that flow into the output tr and internal pull-up resistors. parameter symbol pin/remarks conditions specification v dd [v] min. typ. max. unit normal mode consumption current (note 10-1) iddop(1) vdd1 ? fmhrc=40mhz oscillation mode ? system clock set to high-speed rc, 10mhz (1/4 of 40mhz) ? medium-speed rc oscillation stopped ? system clock frequency division ratio set to 1/1 4.5 to 5.5 7.8 14 ma iddop(2) 2.7 to 3.6 4.9 9.4 iddop(3) ? fmhrc=20mhz oscillation mode ? system clock set to high-speed rc, 10mhz (1/2 of 20mhz) ? medium-speed rc oscillation stopped ? system clock frequency division ratio set to 1/1 4.5 to 5.5 7.1 12.8 iddop(4) 2.7 to 3.6 4.5 8.6 iddop(5) ? high-speed rc oscillation stopped ? system clock set to medium-speed rc oscillation mode ? system clock frequency division ratio set to 1/2 4.5 to 5.5 0.60 1.9 iddop(6) 2.7 to 3.6 0.38 1.3 halt mode consumption current (note 10-1) iddhalt(1) halt mode ? fmhrc=40mhz oscillation mode ? system clock set to high-speed rc, 10mhz(1/4 of 40mhz) ? medium-speed rc oscillation stopped ? system clock frequency division ratio set to 1/1 4.5 to 5.5 3.2 5.0 iddhalt(2) 2.7 to 3.6 2.0 3.1 iddhalt(3) halt mode ? fmhrc=20mhz oscillation mode ? system clock set to high-speed rc, 10mhz (1/2 of 20mhz) ? medium-speed rc oscillation stopped ? system clock frequency division ratio set to 1/1 4.5 to 5.5 2.5 3.9 iddhalt(4) 2.7 to 3.6 1.6 2.5 iddhalt(5) halt mode ? high-speed rc oscillation stopped ? system clock set to medium-speed rc oscillation mode ? system clock frequency division ratio set to 1/2 4.5 to 5.5 0.32 1.0 iddhalt(6) 2.7 to 3.6 0.16 0.55 hold mode consumption current (note 10-1) iddhold(1) hold mode ? ta= ? 10 to +50 ? c 4.5 to 5.5 0.04 3.0 ? ? ta= ? 40 to +85 ? c 4.5 to 5.5 0.04 34 iddhold(4) 2.7 to 3.6 0.02 22 iddhold(5) hold mode ? lvd option selected ? ta= ? 10 to +50 ? c 4.5 to 5.5 3.1 6.8 iddhold(6) 2.7 to 3.6 2.4 4.2 iddhold(7) hold mode ? lvd option selected ? ta= ? 40 to +85 ? c 4.5 to 5.5 3.1 39 iddhold(8) 2.7 to 3.6 2.4 25 iddhold(9) hold mode ? watchdog timer active ? ta= ? 10 to +50 ? c 4.5 to 5.5 3.4 10 iddhold(10) 2.7 to 3.6 1.7 6.0 iddhold(11) hold mode ? watchdog timer active ? ta= ? 40 to +85 ? c 4.5 to 5.5 3.4 42 iddhold(12) 2.7 to 3.6 1.7 27 iddhold(13) hold mode ? comparator active (in+=v dd , in ? =v ss ) 4.5 to 5.5 110 160 iddhold(14) 2.7 to 3.6 65 100
lc87f2708a no.a1335-19/24 11. f-rom programming characteristics at ta=+10 to +55 ? c, v ss 1=0v parameter symbol pin/remarks conditions specification vdd[v] min. typ. max. unit onboard programming current iddfw vdd1 ? microcontroller consumption current is excluded. 3.0 to 5.5 5 10 ma programming time tfw(1) ? erase operation 3.0 to 5.5 20 30 ms tfw(2) ? programming operation 40 60 ? 12. power pin treatment re commendations (vdd1, vss1) connect bypass capacitors that meet the follo wing conditions between the vdd1 and vss1 pins: ? connect among the vdd1 and vss1 pins and bypass capacitors c1 and c2 with the shortest possible heavy lead wires, making sure that the impedances between the both pins and the bypass capacitors are as equal as possible (l1=l1', l2=l2'). ? connect a large-capacity capacitor c1 and a small-capacity capacitor c2 in parallel. the capacitance of c2 should be approximately 0.1 ? f. vss1 vdd1 l1? l2? l1 l2 c1 c2
lc87f2708a no.a1335-20/24 figure 1 ac timing measurement point figure 2 oscillation stabilization times power res# medium-speed rc oscillation high-speed rc oscillation operating mode reset time tmshrc unpredictable reset instruction execution reset time and oscillation stabilization time v dd operating v dd lower limit 0v medium-speed rc oscillation high-speed rc oscillation state hold/halt release signal no hold release signal hold release signal valid hold release signal and oscillation stabilization time hold halt instruction execution tmshrc halt release signal valid 0.5v dd
lc87f2708a no.a1335-21/24 note: the external peripheral circuit differs depending on the way in which the power-on reset a nd low-voltage detection reset functions are used. refer to the chapter, entitled "reset function," of the user's manual. figure 3 sample reset circuit figure 4 serial i/o waveforms figure 5 pulse input timing signal waveform tpil tpih di0 di7 di2 di3 di4 di5 di6 do0 do7 do2 do3 do4 do5 do6 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo c res v dd r res res#
lc87f2708a no.a1335-22/24 figure 6 example of por only (lvd deselected) mode waveforms (at reset pin with r res pull-up resistor only) ? the por circuit generates a reset signal only when the power voltage is raised from the vss level. ? no stable reset signal is generated if power is turned on again when the power voltage does not go down to the vss level as shown in (a). if this case is anticipated, use the lvd function as explained below or configure an external reset circuit. ? a reset is effected only when power is turned on again after the power voltage goes down to and remains at the vss level for 100 ? s or longer as shown in (b). figure 7 example of por + lvd mode waveforms (at reset pin with r res pull-up resistor only) ? a reset is effected both when power is turned on and when it goes down. ? the hysteresis width (lvhys) is introduced in the lvd circuit to prevent the iterations of the ic entering and exiting the reset state near the detection threshold level. v dd res# lvd hysteresis width (lvhys) lvd voltage (lvdet) reset unknown area (lvuks) reset period reset period reset period lvd release voltage (lvdet+lvhys) por release voltage (porrl) v dd res# reset unknown area (pouks) (a) (b) reset period reset period 100 ? s or longer
lc87f2708a no.a1335-23/24 figure 8 minimum low voltage detection width (example of short interruption of power/ power fluctuation waveform) v dd lvd voltage tlvdw v ss lvd release voltage lvdet-0.5v
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